? 2005 fairchild semiconductor corporation ds500581 www.fairchildsemi.com may 2002 revised june 2005 74lcxh16245 low voltage 16-bit bidirectional transceiver with bushold 74lcxh16245 low voltage 16-bit bidirectional transceiver with bushold general description the lcxh16245 contains sixteen non-inverting bidirec- tional buffers with 3-state outputs and is intended for bus oriented applications. the device is designed for low volt- age (2.5v or 3.3v) v cc applications with capability of inter- facing to a 5v signal environment. the device is byte controlled. each byte has separate control inputs which could be shorted together for full 16-bit operation. the t/r inputs determine the direction of data flow through the device. the oe inputs disable both the a and b ports by placing them in a high impedance state. the lcxh16245 data inputs include active bushold cir- cuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. the lcxh16245 is fabricated with an advanced cmos technology to achieve high speed operation while maintain- ing cmos low power dissipation. features 2.3v?3.6v v cc specifications provided 4.5 ns t pd max (v cc 3.3v), 20 p a i cc max power-down high impedance outputs bushold on inputs eliminates the need for external pull-up/pull-down resistors r 24 ma output drive (v cc 3.0v) implements patented noise/emi reduction circuitry latch-up performance conforms to the requirements of jesd78 esd performance: human body model ! 2000v machine model ! 200v also packaged in plastic fine-pitch ball grid array (fbga) ordering code: note 1: ordering code ? g ? indicates trays. note 2: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. logic symbol order number package number package description 74lcxh16245g (note 1) (note 2) bga54a 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide 74lcxh16245mtd (note 2) mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 74lcxh16245 connection diagrams pin assignment for ssop and tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments truth tables h high voltage level l low voltage level x immaterial z high impedance logic diagram pin names description oe n output enable input t/r n transmit/receive input a 0 ? a 15 side a inputs or 3-state outputs (bushold) b 0 ? b 15 side b inputs or 3-state outputs (bushold) 123456 a b 0 nc t/r 1 oe 1 nc a 0 b b 2 b 1 nc nc a 1 a 2 c b 4 b 3 v cc v cc a 3 a 4 d b 6 b 5 gnd gnd a 5 a 6 e b 8 b 7 gnd gnd a 7 a 8 f b 10 b 9 gnd gnd a 9 a 10 g b 12 b 11 v cc v cc a 11 a 12 h b 14 b 13 nc nc a 13 a 14 j b 15 nc t/r 2 oe 2 nc a 15 inputs outputs oe 1 t/r 1 llbus b 0 ? b 7 data to bus a 0 ? a 7 lhbus a 0 ? a 7 data to bus b 0 ? b 7 h x high z state on a 0 ? a 7 , b 0 ? b 7 inputs outputs oe 2 t/r 2 l l bus b 8 ? b 15 data to bus a 8 ? a 15 l h bus a 8 ? a 15 data to bus b 8 ? b 15 h x high z state on a 8 ? a 15 , b 8 ? b 15
3 www.fairchildsemi.com 74lcxh16245 absolute maximum ratings (note 3) recommended operating conditions (note 5) note 3: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maxi mum ratings. the ? recom- mended operating conditions ? table will define the conditions for actual device operation. note 4: i o absolute maximum rating must be observed. note 5: floating or unused control inputs must be high or low. dc electrical characteristics symbol parameter value conditions units v cc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to v cc 0.5 v v o dc output voltage 0.5 to 7.0 output in 3-state v 0.5 to v cc 0.5 output in high or low state (note 4) i ik dc input diode current 50 v i gnd ma i ok dc output diode current 50 v o gnd ma 50 v o ! v cc i o dc output source/sink current r 50 ma i cc dc supply current per supply pin r 100 ma i gnd dc ground current per ground pin r 100 ma t stg storage temperature 65 to 150 q c symbol parameter min max units v cc supply voltage operating 2.0 3.6 v data retention 1.5 3.6 v i input voltage 0v cc v v o output voltage high or low state 0 v cc v 3-state 0 v cc i oh /i ol output current v cc 3.0v 3.6v r 24 ma v cc 2.7v 3.0v r 12 v cc 2.3v 2.7v r 8 t a free-air operating temperature 40 85 q c ' t/ ' v input edge rate, v in 0.8v ? 2.0v, v cc 3.0v 0 10 ns/v symbol parameter conditions v cc t a 40 q c to 85 q c units (v) min max v ih high level input voltage 2.3 2.7 1.7 v 2.7 3.6 2.0 v il low level input voltage 2.3 2.7 0.7 v 2.7 3.6 0.8 v oh high level output voltage i oh 100 p a2.3 3.6 v cc 0.2 v i oh 8 ma 2.3 1.8 i oh 12 ma 2.7 2.2 i oh 18 ma 3.0 2.4 i oh 24 ma 3.0 2.2 v ol low level output voltage i ol 100 p a2.3 3.6 0.2 v i ol 8ma 2.3 0.6 i ol 12 ma 2.7 0.4 i ol 16 ma 3.0 0.4 i ol 24 ma 3.0 0.55 i i input leakage current data v i v cc or gnd 2.3 3.6 r 5.0 p a control o d v i d 5.5 2.3 3.6 r 5.0
www.fairchildsemi.com 4 74lcxh16245 dc electrical characteristics (continued) note 6: an external driver must source at least the specified current to switch from low-to-high. note 7: an external driver must sink at least the specified current to switch from high-to-low. ac electrical characteristics note 8: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. dynamic switching characteristics capacitance symbol parameter conditions v cc t a 40 q c to 85 q c units (v) min max i i(hold) bushold input minimum v in 0.7v 2.3 45 p a drive hold current v in 1.7v 45 v in 0.8v 3.0 75 v in 2.0v 75 i i(od) bushold input over-drive (note 6) 2.7 300 p a current to change state (note 7) 300 (note 6) 3.6 450 (note 7) 450 i oz 3-state i/o leakage v o v cc or gnd 2.3 3.6 r 5.0 p a i off power-off leakage current v i or v o 5.5v 0 10 p a i cc quiescent supply current v i v cc or gnd 2.3 ? 3.6 20 p a ' i cc increase in i cc per input v ih v cc 0.6v 2.3 ? 3.6 500 p a symbol parameter t a 40 q c to 85 q c, r l 500 : units v cc 3.3v r 0.3v v cc 2.7v v cc 2.5v r 0.2v c l 50 pf c l 50 pf c l 30 pf min max min max min max t phl propagation delay 1.0 4.5 1.0 5.2 1.0 5.4 ns t plh a n to b n or b n to a n 1.04.51.05.21.05.4 t pzl output enable time 1.0 6.5 1.0 7.2 1.0 8.5 ns t pzh 1.06.51.07.21.08.5 t plz output disable time 1.0 6.4 1.0 6.9 1.0 7.7 ns t phz 1.06.41.06.91.07.7 t oshl output to output skew (note 8) 1.0 ns t oslh 1.0 symbol parameter conditions v cc (v) t a 25 q c units typ ical v olp quiet output dynamic peak v ol c l 50 pf, v ih 3.3v, v il 0v 3.3 0.8 v c l 30 pf, v ih 2.5v, v il 0v 2.5 0.6 v olv quiet output dynamic valley v ol c l 50 pf, v ih 3.3v, v il 0v 3.3 0.8 v c l 30 pf, v ih 2.5v, v il 0v 2.5 0.6 symbol parameter conditions typical units c in input capacitance v cc open, v i 0v or v cc 7pf c i/o input/output capacitance v cc 3.3v, v i 0v or v cc 8pf c pd power dissipation capacitance v cc 3.3v, v i 0v or v cc , f 10 mhz 20 pf
5 www.fairchildsemi.com 74lcxh16245 ac loading and waveforms generic for lcx family figure 1. ac test circuit (c l includes probe and jig capacitance) waveform for inverting and non-inverting functions propagation delay. pulse width and t rec waveforms 3-state output low enable and disable times for logic 3-state output high enable and disable times for logic setup time, hold time and recovery time for logic t rise and t fall figure 2. waveforms (input characteristics; f =1mhz, t r = t f = 3ns) test switch t plh , t phl open t pzl , t plz 6v at v cc 3.3 r 0.3v, 2.7v and v cc x 2 at v cc 2.5 r 0.2v t pzh , t phz gnd symbol v cc 3.3v r 0.3v 2.7v 2.5v r 0.2v v mi 1.5v 1.5v v cc /2 v mo 1.5v 1.5v v cc /2 v x v ol 0.3v v ol 0.3v v ol 0.15v v y v oh 0.3v v oh 0.3v v oh 0.15v
www.fairchildsemi.com 6 74lcxh16245 schematic diagram generic for lcx family
7 www.fairchildsemi.com 74lcxh16245 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a
www.fairchildsemi.com 8 74lcxh16245 low voltage 16-bit bidirectional transceiver with bushold physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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